1. Field
Example embodiments relate to a semiconductor package structure.
2. Description of Related Art
Currently, a semiconductor package structure is fabricated by sequentially stacking a lower package and an upper package to embody high integration thereof. The lower package has a lower chip stacked structure on a lower printed circuit board. The upper package has an upper chip stacked structure on an upper printed circuit board. Each of the lower and upper chip stacked structures has sequentially stacked semiconductor chips. As a result, the semiconductor package structure has a lower printed circuit board, a lower chip stacked structure, an upper printed circuit board and an upper chip stacked structure, which are sequentially stacked.
In such a case, the semiconductor package structure has the upper printed circuit board between the lower chip stacked structure and the upper chip stacked structure, and thus there may be a limit in a process to embody the high integration of the semiconductor package structure. This is because the upper printed circuit board may dispose between the lower chip stacked structure and the upper chip stacked structure to not facilitate a reduction in thickness of the semiconductor package structure. In addition, the semiconductor package structure has the lower chip stacked structure between the lower printed circuit board and the upper printed circuit board, and thus there may be a limit in a process to embody the high integration of the semiconductor package structure.
This is because the lower chip stacked structure may have a limited space between the lower printed circuit board and the upper printed circuit board by increasing the stacked number of semiconductor chips, which can increase a process failure rate. Therefore, the semiconductor package structure may not have a process margin for the high integration thereof, and thus it may not satisfy the trend of multi-functionalization.